Device fabrication techniques are sufficiently advanced to permit integration of electronic and optical devices on a single chip. These optoelectronic integrated circuits, referred to as OEICs, have been realized generally with light sources and a small transistor driving using a AlGaAs/GaAs semiconductor system. See H. Choi et al., IEEE Electron Device Letters, Vol. EDL-7, No. 9, pp. 500-2 (1986). More recently, these techniques have been extended to realization of a multiple quantum well (MQW) laser with a field-effect transistor (FET) driver circuit. See S. Yamakoshi, et al., Electronics Letters, Vol. 19, No. 24, pp. 1020-1 (1983).
In general, it is accepted that difficulty exists in integration of optical and electronic devices because of significant differences in layer structures for the optical element and for the electronic element. Yamakoshi et al., cited above, address and design around this problem by creating two distinct levels in the top surface of a semi-insulating substrate: the lower level for accepting growth of the MQW heterostructure laser, and the upper level for accepting growth of the FET driver. A relatively wide groove etched in the semi-insulating substrate is so configured that it permits selective growth of the laser "substrate" layer along the exposed surface of the lower level (the bottom of the groove) as well as continuing up and onto a portion of the upper level. Hence, Yamakoshi et al. have made it possible to grow and interconnect two separate elements as an optoelectronic integrated circuit albeit a substantially hybrid interconnection. As such, the resulting optoelectronic integrated circuit is fabricated in a nonplanar fashion by interconnecting discrete devices grown separately and electrically isolated from one another on the semi-insulating substrate. Primarily of the device is seriously compromised by the two level technique realized by groove formation as required by Yamakoshi et al. for permitting growth of the MQW heterostructure laser.
Alternative fabrication techniques which avoid the necessity for bi-level circuit designs generally involve the use of vertical regions interposed or eliminated between the optical and electronic devices for electrical isolation. See, for example, D. Wake et al., Electronics Letters, Vol. 22, No. 13 pp. 719-21 (1986); J. H. Abeles et al., Electronics Letters, Vol. 23, No. 20, pp. 1037-8 (1987); and U.S. Pat. No. 4,438,447. These techniques require additional processing to form the vertical isolation regions and subsequently establish the appropriate electrical connection between the devices.